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| TC55V4000ST-70,-85 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55V4000ST is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 0.5 A standby current (at VDD = 3 V, Ta = 25C) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC55V4000ST is available in a normal pinout plastic 32-pin thin-small-outline package (TSOP). FEATURES * * * * * * Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Standby Current (maximum): 3.6 V 3.0 V 7 A 5 A * Access Times (maximum): TC55V4000ST -70 Access Time CE Access Time OE Access Time -85 85 ns 85 ns 45 ns 70 ns 70 ns 35 ns * Package: TSOP 32-P-0.50 (ST) (Weight: 0.24 g typ) PIN ASSIGNMENT (TOP VIEW) 32 PIN TSOP 16 1 PIN NAMES A0~A18 R/W OE CE Address Inputs Read/Write Control Output Enable Chip Enable Data Inputs/Outputs Power Ground I/O1~I/O8 VDD GND 17 32 (Normal pinout) Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 5 R/W 21 I/O1 6 A17 22 I/O2 7 A15 23 I/O3 8 VDD 24 GND 9 A18 25 I/O4 10 A16 26 I/O5 11 A14 27 I/O6 12 A12 28 I/O7 13 A7 29 I/O8 14 A6 30 CE 15 A5 31 A10 16 A4 42 OE 2001-11-30 1/10 TC55V4000ST-70,-85 BLOCK DIAGRAM CE A13 A17 A15 A18 A16 A14 A4 A5 A6 A7 A12 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 ROW ADDRESS BUFFER ROW ADDRESS REGISTER ROW ADDRESS DECODER VDD GND MEMORY CELL ARRAY 2,048 x 256 x 8 (4,194,304) 8 DATA CONTROL SENSE AMP COLUMN ADDRESS DECODER CLOCK GENERATOR COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A3 A2 A1 A0 A8 A9 A11 A10 OE R/W CE CE OPERATING MODE MODE Read Write Output Deselect Standby * = don't care H = logic high L = logic low CE OE R/W H L H * Output Input High-Z High-Z I/O1~I/O8 POWER IDDO IDDO IDDO IDDS L L L H L * H * MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~4.6 -0.3*~4.6 -0.5~VDD + 0.5 0.6 260 -55~150 -40~85 UNIT V V V W C C C *: -3.0 V when measured at a pulse width of 50ns 2001-11-30 2/10 TC55V4000ST-70,-85 DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C) 2.3 V~3.6 V SYMBOL PARAMETER MIN VDD VIH VIL VDH *: Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage 2.3 2.2 -0.3* 1.5 TYP 3.0 MAX 3.6 VDD + 0.3 VDD x 0.22 3.6 V V V V UNIT -3.0 V when measured at a pulse width of 50 ns DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 2.3 to 3.6 V) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = VDD - 0.5 V VOL = 0.4 V CE = VIH or OE = VIH or R/W = VIL, VOUT = 0 V~VDD CE = VIL and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL TEST CONDITION MIN -0.5 2.1 min 1 s tcycle min 1 s TYP 0.05 MAX UNIT 1.0 1.0 50 mA 10 45 mA 5 3 0.6 6 0.7 7 0.5 1 5 A mA A mA mA A lDDO1 Operating Current lDDO2 CE = 0.2 V and R/W = VDD - 0.2 V, IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V CE = VIH VDD = 3.0 V 10% lDDS1 VDD = 3.0 V 10% VDD = 3.3 V 0.3 V Ta = 25C Ta = -40~85C Ta = 25C Ta = -40~85C Ta = 25C Standby Current lDDS2 CE = VDD - 0.2 V, VDD = 1.5 V~3.6 V VDD = 3 V Ta = -40~40C Ta = -40~85C CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not 100% tested. 2001-11-30 3/10 TC55V4000ST-70,-85 (Ta = -40 to 85C, VDD = 2.7 to 3.6 V) READ CYCLE TC55V4000ST SYMBOL PARAMETER MIN tRC tACC tCO tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 70 5 0 10 -70 MAX 70 70 35 30 30 MIN 85 5 0 10 -85 MAX 85 85 45 35 35 ns UNIT AC CHARACTERISTICS AND OPERATING CONDITIONS WRITE CYCLE TC55V4000ST SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 70 50 60 0 0 0 30 0 -70 MAX 25 MIN 85 55 70 0 0 0 35 0 -85 MAX 35 ns UNIT AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 30 pF + 1 TTL Gate 0.4 V, 2.4 V VDD x 0.5 VDD x 0.5 5 ns 2001-11-30 4/10 TC55V4000ST-70,-85 (Ta = -40 to 85C, VDD = 2.3 to 3.6 V) READ CYCLE TC55V4000ST SYMBOL PARAMETER MIN tRC tACC tCO tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 85 5 0 10 -70 MAX 85 85 45 35 35 MIN 100 5 0 10 -85 MAX 100 100 50 40 40 ns UNIT AC CHARACTERISTICS AND OPERATING CONDITIONS WRITE CYCLE TC55V4000ST SYMBOL PARAMETER MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 85 55 70 0 0 0 40 0 -70 MAX 35 MIN 100 60 80 0 0 0 40 0 -85 MAX 40 ns UNIT AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDD x 0.5 5 ns 2001-11-30 5/10 TC55V4000ST-70,-85 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address tACC tCO CE tOH tOE OE tOD tOEE tCOE DOUT Hi-Z INDETERMINATE VALID DATA OUT tODO Hi-Z WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address tAS R/W tCW CE tWP tWR tODW DOUT (See Note 2) Hi-Z tDS DIN (See Note 5) tOEW (See Note 3) tDH (See Note 5) VALID DATA IN 2001-11-30 6/10 TC55V4000ST-70,-85 WRITE CYCLE 2 (CE CONTROLLED) (See Note 4) tWC Address tAS R/W tCW CE tWP tWR tCOE DOUT Hi-Z tODW Hi-Z tDS tDH (See Note 5) DIN (See Note 5) VALID DATA IN Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2001-11-30 7/10 TC55V4000ST-70,-85 DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C) SYMBOL VDH PARAMETER Data Retention Supply Voltage VDH = 3.0 V IDDS2 Standby Current Ta = -40~40C Ta = -40~85C MIN 1.5 0 tRC (See Note) TYP MAX 3.6 1 5 7 UNIT V A VDH = 3.6 V Ta = -40~85C tCDR tR Note: Chip Deselect to Data Retention Mode Time Recovery Time Read cycle time ns ns CE CONTROLLED DATA RETENTION MODE VDD VDD DATA RETENTION MODE 4.5 V (See Note) VIH tCDR CE (See Note) tR VDD - 0.2 V GND Note: When CE is operating at the VIH level (2.2V), the standby current is given by IDDS1 during the transition of VDD from 3.6 to 2.4V. 2001-11-30 8/10 TC55V4000ST-70,-85 PACKAGE DIMENSIONS Weight: 0.24 g (typ) 2001-11-30 9/10 TC55V4000ST-70,-85 RESTRICTIONS ON PRODUCT USE 000707EBA * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2001-11-30 10/10 |
Price & Availability of TC55V4000ST-70
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